1. Field of the Invention
The present invention relates to a ferroelectric capacitor, more specifically, a ferroelectric capacitor which is improved ferroelectricity.
2. Description of the Prior Art
A conventional ferroelectric capacitor is shown in FIG. 1. A silicon oxide layer 4 is formed on a silicon substrate 2, then a lower electrode 6 made of platinum is formed thereon. A PZT (PbZr.sub.x Ti.sub.1-x O.sub.3) layer 8 as a ferroelectric layer is formed on the lower layer 6. Further, an upper layer 10 made of platinum is formed thereon. So that, a ferroelectric capacitor is formed by the lower electrode 6, the PZT layer 8 and the upper electrode 10.
The reason why the lower electrode 6 is made by platinum is as follows. The PZT layer 8 must be formed on a layer which is oriented axially or which has mono-crystal for obtaining better matching of lattice constant. When the PZT layer 8 is formed on an amorphous layer, ferroelectricity of the PZT layer is decreased because the amorphous layer is a layer which is not oriented axially. On the other hand, the lower electrode 6 must be formed under insulated condition from the silicon substrate 2. So that, the silicon oxide layer 4 is formed on the silicon substrate 2. Also the silicon oxide layer 4 is made of amorphous. Generally, a layer formed on amorphous becomes as a layer which is not oriented axially. However, platinum has a characteristics that becomes a layer which is oriented axially even when it is formed on amorphous. Therefore, platinum is utilized for the lower electrode 6.
FIG. 3A illustrates a structure of a memory device which is proposed by using a ferroelectric capacitor. A source region 104 and a drain region 106 are formed in the silicon substrate 102, a gate electrode 108 is formed on the channel region. A plug 110 made of poly silicon is formed on the drain region 106 of this transistor structure. Further, a platinum layer 112 is formed on the poly silicon plug 110, also PZT layer 114 is formed thereon as ferroelectic material. Further, a platinum layer 116 is formed on the PZT layer 114. So that, the memory device is formed.
Because of manufacturing process of PZT is totally different from that of transistor, the platinum layer 112, PZT layer 114, the platinum layer 116 are formed on the poly silicon plug 110 as shown in the figure.
The conventional ferroelectric capacitor shown in FIG. 1 has following issues to resolve. At first, it is depending on kind and composition of the ferroelectric material, a possibility of mismatching for lattice constant between the ferroelectric material and the platinum layer formed as the lower electrode is increased, so that ferroelectricity of the capacitor is possibly degraded.
Subsequently, platinum has a characteristics that oxygen goes though it easily, so that oxygen contained in the ferroelectric material (such as PZT) leaks therefrom. Therefore, degradation for retention property and fatigue property beside repeated polarization reverse is caused. That is, oxygen contained in the ferroelectric material leaks through columnar crystal structure of platinum as shown in FIG. 2.
It is necessary to resolve following issues to realize a conventional memory device shown in FIG. 3A.
In FIG. 3A, the platinum layer 112 is formed directly on the poly silicon plug 110. So that, platinum and poly silicon cause chemical reaction, then silicide is formed. Once silicide is formed, it is not possible to obtain high ferroelectricity. Even if a ferroelectric layer is formed thereon, because of lattice constant between silicide and the ferroelectric layer is totally different each other. Also, since surface of the poly silicon plug 110 has roughness, platinum formed on the poly silicon plug 110 can not be oriented. Therefore, the ferroelectric layer formed thereon does not have high ferroelectricity. FIG. 3B shows a hysteresis curve of PZT formed on platinum which is formed on poly silicon. As it is clear from the figure, remanent polarization Pr is almost disappeared from the figure. The same issue is observed when tungsten is used as the plug.
To resolve above described problems, there is a case that a tantalum layer which does not react with the platinum layer 112 is formed on the poly silicon plug 110, then the platinum layer 112 is formed thereon. According to above way, it is possible to prevent forming polycide as a result of chemical reaction of platinum and poly silicon, also better ferroelectricity can be observed due to improvement of orientation for the ferroelectric layer. However, surface of the tantalum layer 113 maintains roughness of the surface of the poly silicon plug 110, as shown in FIG. 4A. Therefore, platinum formed thereon can not be oriented axially. So that, the ferroelectric layer formed on the platinum does not have high ferroelectricity. Also, there is a issue that tantalum oxide is formed in a boundary between the poly silicon plug 110 and the tantalum layer 113 caused by thermal treatment. Therefore, dielectric constant of the memory device is decreased.